BIT ERROR DETECTOR FOR ITERATIVE ECC DECODER

Patent №

US 7,793,201

Granted

2010-09-07

Filed 2007

Owner

MAXTOR CORPORATION

Lab

AI components

1

ml

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

11620400

An iterative decoder includes at respective variable nodes, that is, at nodes that correspond to the bits of the code word, bit error detectors that after convergence determine if the respective hard decision bit values have changed from the bit values provided by the channel. The change in value for a given bit indicates that a bit error has been corrected. The bit error detector, for message-passing decoders that perform calculations by addition rather than multiplication, can be readily implemented as an XOR gate. Thus, a bit error is detected at the variable node by XOR'ing the sign bits of the input symbol and the variable node sum. After convergence, the output values produced by the bit error detectors at the respective variable nodes are added together using an adder tree that accumulates the detected bit errors for an entire date block, or ECC code word. Alternatively, the system may group the bits into respective code word symbols and combine the bit error values into symbols-with-errors values using, for example, XOR sub-trees that produce, for each symbol, a single error value. The error value for a given symbol indicates that the symbol is either error-free or includes one or more bit errors, and a total count of the symbols with errors is produced by adding the error values together.

Machine learningH03M 13/612H03M 13/015H03M 13/1111H03M 13/3738

AI classification

Machine learning0.72
AI hardware0.19
Natural language0.01
Vision0.00
Planning0.00
Evolutionary computation0.00
Knowledge representation0.00
Speech0.00

Ownership

MAXTOR CORPORATION

assignment · 187170051

Assignors

ULRIKSSON, BENGT A.

On an employer assignment, the assignors are typically the inventors.

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