COORDINATING ACCESS TO MEMORY LOCATIONS FOR HARDWARE TRANSACTIONAL MEMORY TRANSACTIONS AND SOFTWARE TRANSACTIONAL MEMORY TRANSACTIONS
Patent №
US 7,809,903
Granted
2010-10-05
Filed 2005
Owner
INTEL CORPORATION
Lab
—
AI components
1
planning
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
11303529
Provided is a method, system, and program for coordinating access to memory locations for hardware transactional memory transactions and software transactional memory transactions. A hardware transaction executing in hardware transactional memory initiates a request to access a memory location. A fault is returned to the hardware transaction request in response to an operation by one software transaction executing in a software transactional memory.
AI classification
Ownership
INTEL CORPORATION
assignment · 173890939
Assignors
ADL-TABATABAI, ALI-REZA, SAHA, BRATIN, HUDSON, RICHARD L., AKKARY, HAITHAM, RAJWAR, RAVI
On an employer assignment, the assignors are typically the inventors.