METHOD AND SYSTEM FOR DESIGNING AN ELECTRONIC CIRCUIT

Patent №

US 7,900,182

Granted

2011-03-01

Filed 2008

Owner

—

Lab

—

AI components

evo

Assignment

None on record

Dataset

AIPD

2023_r1 edition

Application

12255819

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A method and system of designing an electronic circuit includes dividing a chip area of a design into a plurality of bins, identifying a candidate bin in the plurality of bins, and performing an area reduction on the candidate bin.

Evolutionary computationG06F 30/39

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Evolutionary computation0.87

Planning0.13

Machine learning0.02

AI hardware0.01

Natural language0.00

Knowledge representation0.00

Speech0.00

Vision0.00

Cites (6)

METHOD FOR PERFORMING TIMING CLOSURE ON VLSI CHIPS IN A DISTRIBUTED ENVIRONMENTUS 7,178,120 · 2007 METHOD AND APPARATUS FOR APPLYING FINE-GRAINED TRANSFORMS DURING PLACEMENT SYNTHESIS INTERACTIONUS 7,047,163 · 2006 METHOD FOR DESIGN OPTIMIZATION USING LOGICAL AND PHYSICAL INFORMATIONUS 6,557,145 · 2003 TIMING-DRIVEN GLOBAL PLACEMENT BASED ON GEOMETRY-AWARE TIMING BUDGETSUS 6,480,991 · 2002 METHOD FOR DESIGN OPTIMIZATION USING LOGICAL AND PHYSICAL INFORMATIONUS 6,286,128 · 2001 METHOD FOR CELL SWAPPING TO IMPROVE PRE-LAYOUT TO POST-LAYOUT TIMINGUS 6,272,668 · 2001

Cited by (2)

CRITICAL REGION IDENTIFICATIONUS 10,140,414 · 2018 ANALYZING SPARSE WIRING AREAS OF AN INTEGRATED CIRCUIT DESIGNUS 8,949,755 · 2015

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