METHODS OF FORMING FIELD EFFECT TRANSISTORS, METHODS OF FORMING FIELD EFFECT TRANSISTOR GATES, METHODS OF FORMING INTEGRATED CIRCUITRY COMPRISING A TRANSISTOR GATE ARRAY AND CIRCUITRY PERIPHERAL TO THE GATE ARRAY, AND METHODS OF FORMING INTEGRATED CIRCUITRY COMPRIS

Patent №

US 7,902,028

Granted

2011-03-08

Filed 2010

Owner

Lab

AI components

1

planning

Assignment

None on record

Dataset

AIPD

2023_r1 edition

Application

12724589

The invention includes methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates. In one implementation, a method of forming a field effect transistor includes forming masking material over semiconductive material of a substrate. A trench is formed through the masking material and into the semiconductive material. Gate dielectric material is formed within the trench in the semiconductive material. Gate material is deposited within the trench in the masking material and within the trench in the semiconductive material over the gate dielectric material. Source/drain regions are formed. Other aspects and implementations are contemplated.

PlanningH10D 84/038H10D 64/027H10D 64/513H10D 64/518H10D 84/0142H10D 84/0144H10D 84/016

AI classification

Planning0.91
Natural language0.00
Vision0.00
AI hardware0.00
Speech0.00
Evolutionary computation0.00
Knowledge representation0.00
Machine learning0.00
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