OMNIBUS LOGIC ELEMENT FOR PACKING OR FRACTURING

Patent №

US 7,911,230

Granted

2011-03-22

Filed 2009

Owner

—

Lab

—

AI components

hardware

Assignment

None on record

Dataset

AIPD

2023_r1 edition

Application

12425342

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Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can be configured to implement register packing and/or a fracturable look up table.

AI hardwareH03K 19/17728G06F 5/01G06F 7/50H03K 19/017581

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Cites (42)

OMNIBUS LOGIC ELEMENTUS 7,671,625 · 2010 LOGIC CELL SUPPORTING ADDITION OF THREE BINARY WORDSUS 7,565,388 · 2009 OMNIBUS LOGIC ELEMENTUS 7,538,579 · 2009 LOGIC CIRCUITRY WITH SHARED LOOKUP TABLEUS 7,317,330 · 2008 SYSTEMS AND METHODS FOR REDUCING STATIC AND TOTAL POWER CONSUMPTION IN A PROGRAMMABLE LOGIC DEVICEUS 7,188,266 · 2007 ARITHMETIC STRUCTURES FOR PROGRAMMABLE LOGIC DEVICESUS 7,185,035 · 2007 OMNIBUS LOGIC ELEMENT INCLUDING LOOK UP TABLE BASED LOGIC ELEMENTSUS 7,167,022 · 2007 FRACTURABLE LOOKUP TABLE AND LOGIC ELEMENTUS 6,943,580 · 2005 FRACTURABLE INCOMPLETE LOOK UP TABLE FOR AREA EFFICIENT LOGIC ELEMENTSUS 6,888,373 · 2005 LOGIC CIRCUITRY WITH SHARED LOOKUP TABLEUS 6,798,240 · 2004 TILEABLE FIELD-PROGRAMMABLE GATE ARRAY ARCHITECTUREUS 6,744,278 · 2004 CUSTOMIZABLE AND PROGRAMMABLE CELL ARRAYUS 6,642,744 · 2003 CONFIGURABLE LOOKUP TABLE FOR PROGRAMMABLE LOGIC DEVICESUS 6,400,180 · 2002 VARIABLE GRAIN ARCHITECTURE FOR FPGA INTEGRATED CIRCUITSUS 6,380,759 · 2002 PROGRAMMABLE LOGIC DEVICE WITH HIGHLY ROUTABLE INTERCONNECTUS 6,294,928 · 2001 FPGA architecture with deep look-up table ramsUS 6,288,568 · 2001 Logic structure and circuit for fast carryUS 6,288,570 · 2001 SEMICONDUCTOR DEVICEUS 6,236,229 · 2001 HYBRID PRODUCT TERM AND LOOK-UP TABLE-BASED PROGRAMMABLE LOGIC DEVICE WITH IMPROVED SPEED AND AREA EFFICIENCYUS 6,201,408 · 2001 Method for implementing large multiplexers with FPGA lookup tablesUS 6,191,610 · 2001 DRIVER CIRCUITRY FOR PROGRAMMABLE LOGIC DEVICES WITH HIERARCHICAL INTERCONNECTION RESOURCESUS 6,191,611 · 2001 METHOD FOR IMPLEMENTING LARGE MULTIPLEXERS WITH FPGA LOOKUP TABLESUS 6,118,300 · 2000 CONFIGURABLE LOGIC ELEMENT WITH ABILITY TO EVALUATE FIVE AND SIX INPUT FUNCTIONSUS 6,051,992 · 2000 METHOD FOR PARALLEL-EFFICIENT CONFIGURING AN FPGA FOR LARGE FFTS AND OTHER VECTOR ROTATION COMPUTATIONSUS 6,021,423 · 2000 ARCHITECTURES FOR PROGRAMMABLE LOGIC DEVICESUS 5,999,016 · 1999

and 17 more

Cited by (7)

OMNIBUS LOGIC ELEMENTUS 10,177,766 · 2019 OMNIBUS LOGIC ELEMENTUS 9,496,875 · 2016 OMNIBUS LOGIC ELEMENTUS 8,878,567 · 2014 OMNIBUS LOGIC ELEMENT FOR PACKING OR FRACTURINGUS 8,593,174 · 2013 LOGIC STRUCTURES FOR TERNARY ADDITION IN LOGIC DEVICESUS 8,482,312 · 2013

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