Patent №
US 7,930,673
Granted
2011-04-19
Filed 2008
Owner
MAGMA DESIGN AUTOMATION, INC.
+1 more
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
12128554
A power optimization method of deriving gated circuitry in a synthesized netlist of an integrated circuit (IC) design is provided. A block in the synthesized netlist is identified as an idle candidate block. Sub-blocks on the chip are clustered into a cluster. For the cluster, a clock gating structure optimized for power savings is determined, based on the idle candidate block. One or more inflexible clock gates are inserted in the netlist according to the clock gate structure.
AI classification
Ownership
MAGMA DESIGN AUTOMATION, INC.
assignment · 212550781
SYNOPSYS, INC.
assignment · 282690807
Assignors
JIANG, YUNJIAN (WILLIAM), SRINIVASAN, ARVIND, BANERJEE, JOY, LI, YINGHUA, DAS, PARTHA, CHAUDHURI, SAMIT
On an employer assignment, the assignors are typically the inventors.