PERFORMING DIRECT CACHE ACCESS TRANSACTIONS BASED ON A MEMORY ACCESS DATA STRUCTURE

Patent №

US 7,937,534

Granted

2011-05-03

Filed 2005

Owner

INTEL CORPORATION

Lab

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

11323262

Embodiments of an apparatus, method, and system for encoding direct cache access transactions based on a memory access data structure are disclosed. In one embodiment, an apparatus includes memory access logic and transaction logic. The memory access logic is to determine whether to allow a memory access based on a memory access data structure. The transaction logic is to assign direct cache access attributes to a transaction based on the memory access data structure.

AI hardwareG06F 12/0879G06F 12/1036G06F 12/1045G06F 12/1081G06F 13/28G06F 12/0862G06F 12/145

AI classification

AI hardware0.91
Knowledge representation0.03
Planning0.02
Natural language0.01
Evolutionary computation0.00
Machine learning0.00
Speech0.00
Vision0.00

Ownership

INTEL CORPORATION

assignment · 257920791

Assignors

MADUKKARUMUKUMANA, RAJESH SANKARAN, MUTHRASANALLUR, SRIDHAR, HUGGAHALLI, RAMAKRISHNA, ILLIKKAL, RAMESHKUMAR G.

On an employer assignment, the assignors are typically the inventors.

From the same owner

© 2026 NYSGPT2525 LLC