METHOD AND SYSTEM FOR IMPLEMENTING TOP DOWN DESIGN AND VERIFICATION OF AN ELECTRICAL CIRCUIT DESIGN

Patent №

US 7,937,673

Granted

2011-05-03

Filed 2007

Owner

CADENCE DESIGN SYSTEMS, INC.

Lab

AI components

3

kr · planning · hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

11717589

Disclosed is a method and system for performing design and verification using stepwise refinement techniques, which can also include or be referred to as “top-down” design verification. With the present stepwise refinement approach, the electronic design can be acted upon at different levels of abstraction, but with approximately the same level of resolution at each abstraction level. A strong relationship of consistency exists between the successive abstraction levels of the design. On account of this consistency, properties that are established or true at one level of the design remain true for all subsequent levels of abstraction of the design.

AI classification

Planning1.00
Knowledge representation0.90
AI hardware0.74
Machine learning0.00
Natural language0.00
Vision0.00
Evolutionary computation0.00
Speech0.00

Ownership

CADENCE DESIGN SYSTEMS, INC.

assignment · 196540257

Assignors

KURSHAN, ROBERT P., MCMILLAN, KENNETH L.

On an employer assignment, the assignors are typically the inventors.

From the same owner

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