GRAPHICAL PROGRAMS WITH FIFO STRUCTURE FOR CONTROLLER/FPGA COMMUNICATIONS

System and method for communicating between graphical programs executing on respective devices, e.g., a programmable hardware element (PHE) and a controller. The system includes a first node representing a first in, first out (FIFO) structure, and a second node providing a controller interface to the FIFO structure. A first portion of the FIFO is implemented on the PHE, and a second portion of the FIFO is implemented in memory of the controller. The first and second nodes are operable to be included respectively in first and second graphical programs, where the first graphical program is deployable to the PHE, where the second graphical program is deployable to the controller, and where the graphical programs communicate via the FIFO in cooperatively performing a specified task. The FIFO may implement a Direct Memory Access (DMA) FIFO, where at least part of a DMA controller is implemented on or coupled to the PHE.