METHOD AND APPARATUS FOR ALIGNING THE PHASES OF DIGITAL CLOCK SIGNALS

A method and apparatus for aligning the phases of digital clock signals are disclosed. For example, a phase alignment circuit according to one embodiment includes a frequency adjuster comprising a first plurality of inputs, where at least some of the first plurality of inputs are coupled to an output of a digital clock of an integrated circuit, a phase adjuster comprising a second plurality of inputs, where at least some of the second plurality of inputs are coupled to a plurality of outputs of the frequency adjuster, and an XOR gate comprising a third plurality of inputs, each of the third plurality of inputs being coupled to one of the plurality of outputs of the frequency adjuster.