CLOCK DIVIDER

There is provided a true single phase logic clock divider that is configured to selectively divide a clock signal by increments of two, three, four, or six. Because the true single phase logic clock divider is based on true single phase logic instead of static logic, the true single phase logic clock divider is able to reliably divide clock signals that could not reliably be divided by clock dividers based on static logic gates. The true single phase logic clock divider is capable of reliably operating at frequencies of greater than or equal to two gigahertz.