LDPC (LOW DENSITY PARITY CHECK) CODED SIGNAL DECODING USING PARALLEL AND SIMULTANEOUS BIT NODE AND CHECK NODE PROCESSING

Patent №

US 7,958,428

Granted

2011-06-07

Filed 2007

Owner

Lab

AI components

1

kr

Assignment

None on record

Dataset

AIPD

2023_r1 edition

Application

11846761

LDPC (Low Density Parity Check) coded signal decoding using parallel and simultaneous bit node and check node processing. This novel approach to decoding of LDPC coded signals may be described as being LDPC bit-check parallel decoding. In some alternative embodiment, the approach to decoding LDPC coded signals may be modified to LDPC symbol-check parallel decoding or LDPC hybrid-check parallel decoding. A novel approach is presented by which the edge messages with respect to the bit nodes and the edge messages with respect to the check nodes may be updated simultaneously and in parallel to one another. Appropriately constructed executing orders direct the sequence of simultaneous operation of updating the edge messages at both nodes types (e.g., edge and check). For various types of LDPC coded signals, including parallel-block LDPC coded signals, this approach can perform decoding processing in almost half of the time as provided by previous decoding approaches.

Knowledge representationH03M 13/1137H04L 1/005H04L 1/0057

AI classification

Knowledge representation0.94
Vision0.16
AI hardware0.01
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Evolutionary computation0.00
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