METHOD AND APPARATUS FOR SECURE CONTEXT SWITCHING IN A SYSTEM INCLUDING A PROCESSOR AND CACHED VIRTUAL MEMORY

A method and a secure mode controller are provided for controlling context switching between secure and user modes in a processing system including a processor and a memory management unit. The method comprises monitoring the memory management unit to detect a non-cache access to an entry point address that contains a secure mode entry instruction, verifying, in response to detection of the entry point address, that the secure mode entry point instruction is executed by the processor, and enabling context switching from the user mode to the secure mode in response to verifying that the secure mode entry instruction is executed by the processor. Each cache line of an instruction cache and a data cache may have a tag containing a secure bit to identify a secure cache line or a non-secure cache line.