Patent №
US 7,971,029
Granted
2011-06-28
Filed 2009
Owner
FUJITSU LIMITED
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
12638746
A barrier synchronization device for realizing barrier synchronization of at least 2 processor cores belonging to a same synchronization group among a plurality of processor cores is included in a multi-core processor having a plurality of processor cores, and when two or more processor cores in that multi-core processor belong to the same synchronization group, the included barrier synchronization device is used for realizing barrier synchronization.
AI classification
Ownership
FUJITSU LIMITED
assignment · 236730701
Assignors
UNNO, HIDEYUKI, UKAI, MASAKI, DEPETRO, MATTHEW
On an employer assignment, the assignors are typically the inventors.