Patent №
US 7,971,174
Granted
2011-06-28
Filed 2008
Owner
CADENCE DESIGN SYSTEMS, INC.
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
12233414
A circuit design process for the reduction of routing congestion is described. This process includes a block placement operation, an initial pin optimization for the block placement, and global routing based upon the initial pin optimization. Congestion data is generated from the global routing and, in an automated process, the pins are re-optimized, based upon the congestion data. This process can be used as part of a custom layout design process, for example.
AI classification
Ownership
CADENCE DESIGN SYSTEMS, INC.
assignment · 215570180
Assignors
KHALSA, MAHENDRA SINGH, GHOSH, SANJIB, GUPTA, VANDANA, MARWAH, HITESH, FANGARIA, PAWAN
On an employer assignment, the assignors are typically the inventors.