PACKET LATENCY BASED ARBITRATION TECHNIQUE FOR A PACKET SWITCH

Patent №

US 8,014,288

Granted

2011-09-06

Filed 2008

Owner

INTEGRATED DEVICE TECHNOLOGY, INC.

Lab

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

12266377

A packet switch including input ports having various input bandwidths initializes credit values for the input ports. An arbiter of the packet switch selects input ports based on the credit values and routes data packets from the selected input ports to a switch fabric of the packet switch. The switch fabric routes data packets from the selected input ports to output ports of the packet switch. Moreover, the arbiter modifies the credit value of each selected input port based on the latency for routing the data packet from the selected input port to the switch fabric. In this way, the arbiter promotes fairness in routing additional data packets through the packet switch. In some embodiments, the switch fabric includes a buffered crossbar and the arbiter modifies credit values of crosspoints in the buffered crossbar based on the latency for routing data packets from the crosspoints to the output ports.

AI hardwareH04L 49/253H04L 47/10H04L 49/15H04L 49/65

AI classification

AI hardware0.80
Knowledge representation0.12
Speech0.00
Vision0.00
Natural language0.00
Machine learning0.00
Evolutionary computation0.00
Planning0.00

Ownership

INTEGRATED DEVICE TECHNOLOGY, INC.

assignment · 217990064

Assignors

MACADAM, ANGUS DAVID STARR

On an employer assignment, the assignors are typically the inventors.

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