Patent US 8,023,328

A memory device is disclosed. The memory device includes a charge trapping layer, and a substrate underlying the charge trapping layer. The carriers are introduced into the charge trapping layer to make a first memory state, for example, when a positive voltage is applied to the gate. At least one of the carriers is released from the charge trapping layer to make a second memory state, for example, when a negative voltage is applied to the gate.