MODIFYING AN INSTRUCTION STREAM USING ONE OR MORE BITS TO REPLACE AN INSTRUCTION OR TO REPLACE AN INSTRUCTION AND TO SUBSEQUENTLY EXECUTE THE REPLACED INSTRUCTION

A processor comprising fetch logic adapted to fetch instructions from memory and decode logic coupled to the fetch logic and adapted to decode the fetched instructions. If a bit in the decode logic is in a first state, a particular fetched instruction is skipped and a group of one or more instructions is executed in lieu of the particular fetched instruction. If the bit is in a second state, both the group and the particular fetched instruction are executed.