METHOD AND SYSTEM FOR REDUCING INSTRUCTION STORAGE SPACE FOR A PROCESSOR INTEGRATED IN A NETWORK ADAPTER CHIP

Certain embodiments for reducing instruction storage space for a processor integrated in a network adapter chip may include generating MIPS instructions from corresponding new instructions. The new instructions may be in patch code instruction (PCI) format. The new instructions may be decoded and the MIPS instructions may be generated by a MIPS processor within a network adapter chip. Decoding the new instructions may also be referred to as interpreting the new instructions. The new instructions may comprise fewer bits than the generated MIPS instructions. The generated MIPS instructions may be executed by the MIPS processor within the network adapter chip.