EFFICIENT AND CONSISTENT SOFTWARE TRANSACTIONAL MEMORY

Patent №

US 8,060,482

Granted

2011-11-15

Filed 2006

Owner

INTEL CORPORATION

Lab

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

11648012

A method and apparatus for efficient and consistent validation/conflict detection in a Software Transactional Memory (STM) system is herein described. A version check barrier is inserted after a load to compare versions of loaded values before and after the load. In addition, a global timestamp (GTS) is utilized to track a latest committed transaction. Each transaction is associated with a local timestamp (LTS) initialized to the GTS value at the start of a transaction. As a transaction commits it updates the GTS to a new value and sets versions of modified locations to the new value. Pending transactions compare versions determined in read barriers to their LTS. If the version is greater than their LTS indicating another transaction has committed after the pending transaction started and initialized the LTS, then the pending transaction validates its read set to maintain efficient and consistent transactional execution.

AI hardwareG06F 8/458G06F 9/3004G06F 9/30087G06F 9/3834G06F 9/38585G06F 9/3863G06F 9/467

AI classification

AI hardware0.99
Knowledge representation0.05
Natural language0.04
Planning0.01
Evolutionary computation0.00
Machine learning0.00
Vision0.00
Speech0.00

Ownership

INTEL CORPORATION

assignment · 225390816

Assignors

WANG, CHENG, WU, YOUFENG, CHEN, WEI-YU, SAHA, BRATIN, ADL-TABATABAI, ALI-REZA

On an employer assignment, the assignors are typically the inventors.

From the same owner

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