SYSTEMS AND METHODS FOR REDUCED TEST CASE GENERATION

Patent №

US 8,065,640

Granted

2011-11-22

Filed 2007

Owner

CADENCE DESIGN SYSTEMS, INC.

Lab

AI components

2

nlp · hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

11755714

In one embodiment of the invention, a method is disclosed including executing one or more commands of a work script to perform work on a portion of a netlist of an integrated circuit design; receiving an indication of a program fault in a first integrated circuit (IC) design program performing work on the portion of the netlist in response to the one or more commands of the work script; and generating a debug work script associated with the work script in response to the program fault, the debug work script including an identification of the portion of the netlist of the integrated circuit design upon which work was being performed during the program fault.

AI classification

AI hardware0.90
Natural language0.55
Planning0.32
Knowledge representation0.01
Speech0.01
Vision0.00
Evolutionary computation0.00
Machine learning0.00

Ownership

CADENCE DESIGN SYSTEMS, INC.

assignment · 193580540

Assignors

RICHTER, SASCHA, BAYLOR, DENIS

On an employer assignment, the assignors are typically the inventors.

From the same owner

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