Patent №
US 8,090,928
Granted
2012-01-03
Filed 2002
Owner
AIRIP CORP.
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
10184402
In one embodiment of the present invention, a processor includes a scalar computation unit; a vector co-processor coupled to the scalar computation unit; and one or more function-specific engines coupled to the scalar computation unit, where the engines are adapted to minimize data exchange penalties by processing small in-out bit slices.
AI classification
AI hardware1.00
Vision0.00
Speech0.00
Machine learning0.00
Knowledge representation0.00
Evolutionary computation0.00
Natural language0.00
Planning0.00
Ownership
AIRIP CORP.
assignment · 146100114
From the same owner
FFT AND FHT ENGINEUS 7,987,221 · 2011FLEXIBLE PROCESSING SYSTEMUS 7,924,878 · 2011CLOCKING SYSTEM INCLUDING A CLOCK CONTROLLER THAT USES BUFFER FEEDBACK TO VARY A CLOCK FREQUENCYUS 7,398,414 · 2008FLEXIBLE PROCESSING SYSTEMUS 7,187,663 · 2007LOW POWER CLOCKING SYSTEMS AND METHODSUS 7,139,921 · 2006INTEGRATED CMOS HIGH PRECISION PIEZO-ELECTRICALLY DRIVEN CLOCKUS 7,098,748 · 2006PHOTOCARD THAT IS INSERTED INTO A NON-DIGITAL CAMERA TO ENABLE THE NON-DIGITAL CAMERA TO TAKE DIGITAL PHOTOGRAPHIC IMAGESUS 7,023,467 · 2006LOW POWER RECONFIGURABLE SYSTEMS AND METHODSUS 6,990,598 · 2006