MICROPROCESSOR WITH FUSED STORE ADDRESS/STORE DATA MICROINSTRUCTION

A microprocessor includes an instruction translator that translates PUSHF, POP, and MOVSB x86 macroinstructions into multiple microinstructions that include a fused store microinstruction. For PUSHF, first and second microinstructions moves the x86 EFLAGS register into and mask off bits in a temporary register, and the fused store microinstruction stores it to a memory location. For POP, a first microinstruction loads a first memory location value into a temporary register and the fused store microinstruction stores it to the second memory location. For MOVSB, the first microinstruction loads a first memory location operand into a temporary register and the fused store microinstruction stores it to a second memory location. A reorder buffer receives the fused store microinstruction into exactly one entry. In response to the fused store microinstruction, an instruction dispatcher dispatches store address and store data microinstructions, neither of which occupies a reorder buffer entry, to different respective execution units.