POWER STATE TRANSITION INITIATION CONTROL OF MEMORY INTERCONNECT BASED ON EARLY WARNING SIGNAL, MEMORY RESPONSE TIME, AND WAKEUP DELAY
Patent №
US 8,090,967
Granted
2012-01-03
Filed 2008
Owner
INTEL CORPORATION
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
12126540
A proposal for power management control of an interconnect structure based on power state transition control. The power state transition is based on generating early warning signals and an idle timeout value setting based on response time and detection of subsequent requests.
AI classification
AI hardware0.59
Planning0.01
Knowledge representation0.00
Evolutionary computation0.00
Machine learning0.00
Speech0.00
Natural language0.00
Vision0.00
Ownership
INTEL CORPORATION
assignment · 236260365
Assignors
HALLNOR, ERIK G., FANG, ZHEN, ROTITHOR, HEMANT G.
On an employer assignment, the assignors are typically the inventors.
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