SYNTHESIS, PLACE, AND ROUTE RESPONSIVE TO REASONS FOR CRITICAL PATHS NOT MEETING PERFORMANCE OBJECTIVE

Methods are provided for implementing a design of an integrated circuit meeting a performance objective. A timing analysis for the design specifies critical timing paths that do not meet the performance objective. Reasons are determined for the critical timing paths failing to meet the performance objective. A specification of the design is synthesized into a netlist specifying interconnections of primitive elements. The synthesis includes controlling a fanout of a primitive element on each critical timing path failing from excessive fanout. The primitive elements are placed at respective positions, including priority placement of a primitive element on each critical timing path failing from bad placement. The interconnections are routed between the primitive elements at the respective positions. The routing includes priority routing of an interconnection on each critical timing path failing from long routing. A specification of the placed and routed primitive elements is stored.