Patent №
US 8,095,920
Granted
2012-01-10
Filed 2002
Owner
INTEL CORPORATION
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
10245548
The latencies associated with cache misses or other long-latency instructions in a main thread are decreased through the use of a simultaneous helper thread. The helper thread is a speculative prefetch thread to perform a memory prefetch for the main thread. The instructions for the helper thread are dynamically incorporated into the main thread binary during post-pass operation of a compiler.
AI classification
Ownership
INTEL CORPORATION
assignment · 135640857
Assignors
LIAO, STEVE SHIH-WEI, WANG, PERRY H., WANG, HONG, HOFLEHNER, GEROLF F., LAVERY, DANIEL M., SHEN, JOHN P.
On an employer assignment, the assignors are typically the inventors.