GENERATING A HARDWARE DESCRIPTION BASED ON A DIAGRAM WITH STATES AND STATE TRANSITIONS

A system and method for automatically generating a data flow diagram in response to a first diagram. The first diagram may specify one or more states and one or more state transitions, wherein each state transition specifies a transition from a first state to a second state. A data flow diagram may be automatically generated from the first diagram. A hardware description may be generated from the data flow diagram. The hardware description may be usable to configure a programmable hardware element such as, for example, a field-programmable gate array (FPGA). The configured programmable hardware element may implement a hardware implementation of the data flow diagram.