TEST CIRCUIT, PATTERN GENERATING APPARATUS, AND PATTERN GENERATING METHOD

Patent №

US 8,103,464

Granted

2012-01-24

Filed 2008

Owner

NEC ELECTRONICS CORPORATION

Lab

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

12076692

A test circuit connected between a test target circuit and a plurality of external terminals includes N first holding circuits to hold respectively N unit patterns produced by dividing an internal signal pattern to be input to or output from the test target circuit by N, where N is a natural number of two or greater, and a control circuit to make the internal signal pattern held in the N first holding circuits be changed selectively on a unit pattern basis based on a value of an identification signal assigned to each of the unit patterns beforehand, or to make the internal signal pattern held in the N first holding circuits be output selectively on a unit pattern basis based on the values of the identification signal.

AI hardwareG01R 31/31813G01R 31/31917

AI classification

AI hardware0.82
Machine learning0.00
Vision0.00
Evolutionary computation0.00
Knowledge representation0.00
Planning0.00
Natural language0.00
Speech0.00

Ownership

NEC ELECTRONICS CORPORATION

assignment · 207340296

Assignors

SASAKI, YASUO

On an employer assignment, the assignors are typically the inventors.

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