Patent №
US 8,104,007
Granted
2012-01-24
Filed 2008
Owner
CADENCE DESIGN SYSTEMS, INC.
Lab
—
AI components
2
vision · hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
12144651
Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) design layout that includes numerous circuit modules. The method divides the IC design layout into a set of elements, where at least one element includes several wires. The method computes a set of conductivity groups of values for the set of elements. The method identifies a temperature distribution for the IC design layout based on the set of conductivity groups of values. In some embodiments, each of these elements corresponds to a particular portion of a particular layer of the IC design layout. Each element includes several nodes. Each conductivity group of values is defined by entry values. Each entry value describes how heat flow at a particular node of the element is affected by a temperature change at another particular node of the element.
AI classification
Ownership
CADENCE DESIGN SYSTEMS, INC.
assignment · 213920541
Assignors
KARIAT, VINOD, PRAMONO, EDDY, ZHAN, YONG
On an employer assignment, the assignors are typically the inventors.