Patent US 8,166,321

Patent №

US 8,166,321

Granted

Owner

Lab

AI components

1

hardware

Assignment

None on record

Dataset

AIPD

2023_r1 edition

Application

12150386

A coprocessor executing one among a set of candidate kernel loops within an application operates at the minimal clock frequency satisfying schedule constraints imposed by the compiler and data bandwidth constraints. The optimal clock frequency is statically determined by the compiler and enforced at runtime by software-controlled clock circuitry. Power dissipation savings and optimal resource usage are therefore achieved by the adaptation at runtime of the coprocessor clock rate for each of the various kernel loop implementations.

AI hardwareG06F 8/4432G06F 1/08G06F 1/3203G06F 1/324G06F 1/3296Y02D 10/00

AI classification

AI hardware0.99
Knowledge representation0.05
Machine learning0.02
Evolutionary computation0.00
Planning0.00
Natural language0.00
Vision0.00
Speech0.00
© 2026 NYSGPT2525 LLC