PARALLEL DATA PROCESSING APPARATUS

Patent №

US 8,174,530

Granted

2012-05-08

Filed 2007

Owner

CLEARSPEED TECHNOLOGY PLC

Lab

—

AI components

ml · vision · hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

11759205

A data processing apparatus includes a plurality of processing elements arranged in a single instruction multiple data array for processing data relating to graphical primitives. Vertex data relating to graphical primitives is used as feedback data for the processing elements for additional processing.

Machine learning Vision AI hardwareG06F 3/14G09G 5/006G09G 5/363G09G 2360/121

Google Patents

AI classification

Vision0.97

Machine learning0.96

AI hardware0.83

Natural language0.06

Planning0.00

Evolutionary computation0.00

Speech0.00

Knowledge representation0.00

Ownership

CLEARSPEED TECHNOLOGY PLC

assignment · 208750127

Assignors

STUTTARD, DAVE, WILLIAMS, DAVE, O'DEA, EAMON, FAULDS, GORDON, RHOADES, JOHN, CAMERON, KEN, ATKIN, PHIL, WINSER, PAUL, DAVID, RUSSELL, MCCONNELL, RAY, DAY, TIM, GREER, TREY

On an employer assignment, the assignors are typically the inventors.

From the same owner

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Cites (84)

PARALLEL DATA PROCESSING APPARATUSUS 7,802,079 · 2010 PARALLEL DATA PROCESSING APPARATUSUS 7,526,630 · 2009 PARALLEL DATA PROCESSING APPARATUSUS 7,506,136 · 2009 MULTITHREADED SIMD PARALLEL PROCESSOR WITH LOADING OF GROUPS OF THREADSUS 7,447,873 · 2008 MEMORY ACCESS CONSOLIDATION FOR SIMD PROCESSING ELEMENTS HAVING ACCESS INDICATORSUS 7,363,472 · 2008 RENDERING PIPELINEUS 6,697,063 · 2004 PROCESSOR WITH PLURAL ARITHMETIC LOGIC CAPABLE OF PARALLEL OPERATION ON PLURAL SUBOPERANDS IN A REGISTER AND EACH FOR SINGLE OPERATION ON SINGLE SUB-OPERANDUS 6,308,252 · 2001 METHOD AND APPARATUS FOR PERFORMING LATENCY BASED HAZARD DETECTIONUS 6,304,955 · 2001 REGISTER SCOREBOARDING TO SUPPORT OVERLAPPED EXECUTION OF VECTOR MEMORY REFERENCE INSTRUCTIONS IN A VECTOR PROCESSORUS 6,266,759 · 2001 METHOD FOR EFFICIENT HANDLING OF TEXTURE CACHE MISSES BY RECIRCULATIONUS 6,259,460 · 2001 METHODS AND APPARATUS FOR DYNAMIC VERY LONG INSTRUCTION WORD SUB-INSTRUCTION SELECTION FOR EXECUTION TIME PARALLELISM IN AN INDIRECT VERY LONG INSTRUCTION WORD PROCESSORUS 6,173,389 · 2001 VIRTUAL REFRESHTM ARCHITECTURE FOR A VIDEO-GRAPHICS CONTROLLERUS 6,154,225 · 2000 DISTRIBUTED INSTRUCTION QUEUEUS 6,112,019 · 2000 LOAD BALANCED IMAGE GENERATIONUS 6,108,460 · 2000 GEOMETRY PROCESSING OF DIGITAL VIDEO MODELS AND IMAGESUS 6,104,842 · 2000 DATA PROCESSING SYNCHRONIZATION WITH AUTOMATIC QUEUINGUS 6,055,579 · 2000 PROGRAMMING A VECTOR PROCESSOR AND PARALLEL PROGRAMMING OF AN ASYMMETRIC DUAL MULTIPROCESSOR COMPRISED OF A VECTOR PROCESSOR AND A RISC PROCESSORUS 6,016,395 · 2000 COORDINATION AND SYNCHRONIZATION OF AN ASYMMETRIC, SINGLE-CHIP, DUAL MULTIPROCESSORUS 5,978,838 · 1999 GEOMETRY PIPELINE IMPLEMENTED ON A SIMD MACHINEUS 5,973,705 · 1999 NON-LINEAR TEXTURE MAP BLENDINGUS 5,949,426 · 1999 IMAGE GENERATION SYSTEMS HAVING PROCESSING ELEMENT ARRAYS WITH DIRECT ELEMENT COMMUNICATIONUS 5,923,338 · 1999 SHARED ACCESS TEXTURING OF COMPUTER GRAPHIC IMAGESUS 5,892,517 · 1999 LINEAR EXPRESSION EVALUATORUS 5,850,489 · 1998 WAVELET TEXTURINGUS 5,831,625 · 1998 IMAGE GENERATION SYSTEM,METHODS AND COMPUTER PROGRAM PRODUCTS USING DISTRIBUTED PROCESSINGUS 5,808,690 · 1998

and 59 more

Cited by (1)

PARALLEL SIGNAL PROCESSING SYSTEM AND METHODUS 10,869,108 · 2020

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