Patent №
US 8,239,797
Granted
2012-08-07
Filed 2008
Owner
CADENCE DESIGN SYSTEMS, INC.
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
12233460
A circuit design process is presented that includes a block placement operation, followed by global routing based upon the initial placement of the blocks. Congestion data is generated from the global routing and, in an automated process, the blocks are placed again based upon the congestion data to reduce the routing congestion of the design. This can be used as part of a custom layout design process, for example.
AI classification
Ownership
CADENCE DESIGN SYSTEMS, INC.
assignment · 215560984
Assignors
GHOSH, SANJIB, GUPTA, VANDANA, MARWAH, HITESH, KHALSA, MAHENDRA SINGH, FANGARIA, PAWAN
On an employer assignment, the assignors are typically the inventors.