Patent №
US 8,250,231
Granted
2012-08-21
Filed 2007
Owner
XELERATED AB
+2 more
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
11722470
A method to reduce buffer capacity in a processor includes giving the data packets admittance to the processor through at least one interface, storing the data packets in at least one input buffer, and using a packet rate shaper outside of a processing pipeline to control flow of the data packets to the pipeline before the data packets enter the pipeline. First and second data packets are given admittance to the pipeline in dependence on cost information per packet that is dependent upon an expected time period of residence of the first data packet in the pipeline. Cost information dependent upon an expected time period of residence of the second data packet in the pipeline differs from said cost information dependent upon the expected time period of residence of the first data packet in the pipeline.
AI classification
Ownership
XELERATED AB
assignment · 201680494
MARVELL INTERNATIONAL LTD.
assignment · 279190053
MARVELL TECHNOLOGY SWEDEN AB
namechg · 279210700
Assignors
BODEN, THOMAS, CARLSTROM, JAKOB
On an employer assignment, the assignors are typically the inventors.