INTEGRATED CIRCUIT TO ENCODE DATA

An integrated circuit configurable to encode data according to a number of coding schemes and to generate cyclic redundancy codes, includes a number of identical specific hardware cells, and each cell includes four outputs for binary signals, four inputs for binary signals, a buffer to delay by one clock period a binary value received on an input and to output a one-clock period delayed binary value, binary adders to perform XOR operations, configurable multiplexers connecting the outputs, the inputs, the buffer and the adders to each other according to several configurable paths, and controllable switch matrices external to each cell and able to electrically connect and disconnect inputs to or from outputs of another cell.