ATOMIC MEMORY OPERATION CACHE PROTOCOL WITH OPPORTUNISTIC COMBINING

Patent №

US 8,380,935

Granted

2013-02-19

Filed 2009

Owner

CRAY INC.

Lab

AI components

2

kr · hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

12484165

An atomic memory operation cache comprises a cache memory operable to cache atomic memory operation data, a write timer, and a cache controller. The cache controller is operable to update main memory with one or more dirty atomic memory operation cache entries stored in the cache memory upon expiration of the write timer, and is further operable to update main memory with one or more dirty atomic memory operation cache entries stored in the cache memory upon eviction of the one or more dirty atomic memory operation cache entries from the cache memory.

Knowledge representationAI hardwareG06F 12/0804G06F 9/3004G06F 9/526G06F 12/0815

AI classification

AI hardware1.00
Knowledge representation0.94
Planning0.26
Natural language0.03
Vision0.00
Machine learning0.00
Evolutionary computation0.00
Speech0.00

Ownership

CRAY INC.

assignment · 230310566

Assignors

ABTS, DENNIS C., SCOTT, STEVEN L.

On an employer assignment, the assignors are typically the inventors.

From the same owner

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