ARCHITECTURE AND METHOD FOR CACHE-BASED CHECKPOINTING AND ROLLBACK

A cache system to compare memory transactions while facilitating checkpointing and rollback is provided. The system includes at least one processor core including at least one cache operating in write-through mode, at least two checkpoint caches operating in write-back mode, a comparison/checkpoint logic, and a main memory. The at least two checkpoint caches are communicatively coupled to the at least one cache operating in write-through mode. The comparison/checkpoint logic is communicatively coupled to the at least two checkpoint caches. The comparison/checkpoint logic compares memory transactions stored in the at least two checkpoint caches responsive to an initiation of a checkpointing. The main memory is communicatively coupled to at least one of the at least two checkpoint caches.