LOW COMPLEXITY FINITE PRECISION DECODERS AND APPARATUS FOR LDPC CODES

Patent №

US 8,458,556

Granted

2013-06-04

Filed 2010

Owner

STMICROELECTRONICS, SA

+2 more

Lab

—

AI components

vision · hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

12900584

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In this invention, a new class of finite precision multilevel decoders for low-density parity-check (LDPC) codes is presented. These decoders are much lower in complexity compared to the standard belief propagation (BP) decoder. Messages utilized by these decoders are quantized to certain levels based on the number of bits allowed for representation in hardware. A message update function specifically defined as part of the invention, is used to determine the outgoing message at the variable node, and the simple min operation along with modulo 2 sum of signs is used at the check node. A general methodology is provided to obtain the multilevel decoders, which is based on reducing failures due to trapping sets and improving the guaranteed error-correction capability of a code. Hence these decoders improve the iterative decoding process on finite length graphs and have the potential to outperform the standard floating-point BP decoder in the error floor region. The description and apparatus of 3-bit decoders for column-weight three LDPC codes is also presented.

Vision AI hardwareH03M 13/1171H03M 13/1117H03M 13/1137H03M 13/114H03M 13/1142H03M 13/3707H03M 13/6577H04L 1/005+1 more

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AI classification

AI hardware1.00

Vision0.75

Machine learning0.28

Speech0.01

Knowledge representation0.00

Planning0.00

Natural language0.00

Evolutionary computation0.00

Ownership

STMICROELECTRONICS, SA

assignment · 251480055

UNIVERSITY OF CERGY-PONTOISE

assignment · 251480055

UNIVERSITY OF ARIZONA

assignment · 251480055

Assignors

PLANJERY, SHIVA K., CHILAPPAGARI, SHASHI KIRAN, VASIC, BANE, DECLERCQ, DAVID

On an employer assignment, the assignors are typically the inventors.

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