HIERARCHICAL ORDER RANKED SIMULATION OF ELECTRONIC CIRCUITS

A method of simulating an integrated circuit design is provided. In this method, a node order ranking of nodes in a netlist can be determined. Circuits of the netlist can then be partitioned based on the node order ranking with both static current driving and dynamic current driving schemes. A hierarchical data structure can be built based on the node order partitioning. In one embodiment, intermediate node orders can be dynamically merged for simulation optimization. Then, the circuits can be re-partitioned based on one or more merged intermediate node orders. Solving and integration can be performed using the hierarchical data structure to generate an order-ranked hierarchy engine. Analysis on the order-ranked hierarchy engine can be performed. At this point, simulation data of the IC design can be exported based on the analysis. By using this method, linear network reduction with its attendant accuracy loss is unnecessary.