THREAD SYNCHRONIZATION IN A MULTI-THREAD NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE

Patent №

US 8,514,874

Granted

2013-08-20

Filed 2010

Owner

LSI CORPORATION

Lab

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

12975880

Described embodiments provide a packet classifier for a network processor that generates tasks corresponding to each received packet. The packet classifier includes a scheduler to generate a thread of contexts for each task received by the packet classifier from a plurality of processing modules of the network processor. The scheduler includes one or more output queues to temporarily store contexts. Each thread corresponds to an order of instructions applied to the corresponding packet, and includes an identifier of a corresponding one of the output queues. The scheduler sends the contexts to a multi-thread instruction engine that processes the threads. An arbiter selects one of the output queues in order to provide output packets to the multi-thread instruction engine, the output packets associated with a corresponding thread of contexts. Each output queue transmits output packets corresponding to a given thread contiguously in the order in which the threads started.

AI hardwareG06F 15/167G06F 9/3851G06F 9/3885H04L 47/2441

AI classification

AI hardware1.00
Knowledge representation0.03
Vision0.01
Planning0.00
Evolutionary computation0.00
Machine learning0.00
Natural language0.00
Speech0.00

Ownership

LSI CORPORATION

assignment · 255350381

Assignors

MITAL, DEEPAK, CLEE, JAMES

On an employer assignment, the assignors are typically the inventors.

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