METHODS, SYSTEMS, AND ARTICLES OF MANUFACTURE FOR IMPLEMENTING CONSTRAINT CHECKING WINDOWS FOR AN ELECTRONIC DESIGN FOR MULTIPLE-PATTERNING LITHOGRAPHY PROCESSES
Patent №
US 8,516,404
Granted
2013-08-20
Filed 2011
Owner
CADENCE DESIGN SYSTEMS, INC.
Lab
—
AI components
4
vision · kr · evo · hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
13341849
Disclosed are method(s), system(s), and article(s) of manufacture for implementing a layout of an electronic circuit using one or more constraint checking windows. The method identifies some constraints on multiple-patterning lithography and multiple constraint checking windows for the layout. The method determines one or more metrics for a constraint checking window or for a layout and assigns one or more shapes in the one or more constraint checking windows to their respective mask designs based on the one or more metrics. The method traverses through the one or more constraint checking windows until all shapes in the layout are assigned to their respective mask designs. The method may also determine a processing order for the one or more constraint checking windows based on the distribution of a type of shapes in the layout.
AI classification
Ownership
CADENCE DESIGN SYSTEMS, INC.
assignment · 274670084
Assignors
CAO, MIN, RUEHL, ROLAND, LAMANT, GILLES S.C.
On an employer assignment, the assignors are typically the inventors.