Patent №
US 8,539,485
Granted
2013-09-17
Filed 2007
Owner
FREESCALE SEMICONDUCTOR, INC.
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
11942813
A first thread enters a polling loop to wait for a signal from a second thread before processing instructions dependent on the polling loop. When entering the polling loop, the first thread sets a reservation for a predetermined memory address. The first thread then executes a reservation-based instruction that can change the execution state of the first thread. Reservation circuitry of the processing device that was executing the first thread monitors the reservation. In the event that the reservation cleared, such as by the second thread modifying data at the predetermined memory address, the first thread is reinstated to its prior execution state. By using a hardware reservation mechanism to monitor for clearing of a set reservation, repeated memory accesses to the memory address by the first thread can be minimized or avoided while in the polling loop and other threads can be allowed to execute at the processing device with reduced interference from the waiting thread.
AI classification
Ownership
FREESCALE SEMICONDUCTOR, INC.
assignment · 201400761
Assignors
SNYDER, MICHAEL D., WHISENHUNT, GARY L.
On an employer assignment, the assignors are typically the inventors.