Patent №
US 8,543,992
Granted
2013-09-24
Filed 2006
Owner
INTEL CORPORATION
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
10585680
A method of compiling code that includes partitioning instructions in the code among a plurality of processors based on memory access latency associated with the instructions is disclosed. According to one aspect of the invention, partitioning instructions includes partitioning memory access dependence chains. Other embodiments are described and claimed.
AI classification
AI hardware1.00
Planning0.01
Speech0.00
Machine learning0.00
Natural language0.00
Evolutionary computation0.00
Knowledge representation0.00
Vision0.00
Ownership
INTEL CORPORATION
assignment · 265860152
Assignors
JIANG, XIAODAN, DAI, JINQUAN
On an employer assignment, the assignors are typically the inventors.
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