POWER CONTROL

Patent №

US 8,559,998

Granted

2013-10-15

Filed 2008

Owner

PICOCHIP DESIGNS LIMITED

Lab

—

AI components

evo

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

12264531

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There is provided a femtocell device for use in connecting a mobile terminal to a communication network, the femtocell device comprising means for implementing a power control procedure in which a target value for a first characteristic of transmissions received from the mobile terminal is set and adjusted based on a quality of service criteria for the transmissions; and wherein the means for implementing the power control procedure operates in a physical layer of the femtocell device.

Evolutionary computationH04W 52/06H04W 52/24H04W 52/265

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Evolutionary computation0.56

Knowledge representation0.00

AI hardware0.00

Natural language0.00

Machine learning0.00

Speech0.00

Planning0.00

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Ownership

PICOCHIP DESIGNS LIMITED

assignment · 222960625

Assignors

SMART, CHRISTOPHER BRIAN

On an employer assignment, the assignors are typically the inventors.

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Cites (58)

METHOD AND APPARATUS FOR ESTIMATING PITCH OF SIGNALUS 7,672,836 · 2010 FAST ROUTER AND HARDWARE-ASSISTED FAST ROUTING METHODUS 7,342,414 · 2008 SYSTEM FOR PROCESSING VLIW WORDS CONTAINING VARIABLE LENGTH INSTRUCTIONS HAVING EMBEDDED INSTRUCTION LENGTH IDENTIFIERSUS 7,302,552 · 2007 SYSTEM, APPARATUS AND METHOD FOR DATA PATH ROUTING CONFIGURABLE TO PERFORM DYNAMIC BIT PERMUTATIONSUS 7,237,055 · 2007 COMMUNICATIONS SYSTEM USING RINGS ARCHITECTUREUS 7,103,008 · 2006 METHODS FOR ROUTING PACKETS ON A LINEAR ARRAY OF PROCESSORSUS 6,961,782 · 2005 VLIW PROCESSOR AND METHOD THEREFORUS 6,892,293 · 2005 METHODS AND APPARATUS TO DYNAMICALLY RECONFIGURE THE INSTRUCTION PIPELINE OF AN INDIRECT VERY LONG INSTRUCTION WORD SCALABLE PROCESSORUS 6,775,766 · 2004 PROCESSOR ISOLATION METHOD FOR INTEGRATED MULTI-PROCESSOR SYSTEMSUS 6,681,341 · 2004 VLIW COMPUTER PROCESSING ARCHITECTURE WITH ON-CHIP DYNAMIC RAMUS 6,631,439 · 2003 VLIW PROCESSOR ACCEPTING BRANCHING TO ANY INSTRUCTION IN AN INSTRUCTION WORD SET TO BE EXECUTED CONSECUTIVELYUS 6,615,339 · 2003 VLIW PROCESSOR FOR EXCHANGING AND INPUTTING SUB-INSTRUCTIONS TO CONTAINERS, AND CODE COMPRESSION DEVICE AND METHOD FOR COMPRESSING PROGRAM CODEUS 6,499,096 · 2002 Efficient direct replacement cell fault tolerant architectureUS 6,408,402 · 2002 APPARATUS AND METHOD FOR SERIAL DATA COMMUNICATION BETWEEN PLURALITY OF CHIPS IN A CHIP SETUS 6,381,293 · 2002 METHOD FOR OPTIMIZING COMMUNICATION SPEED BETWEEN PROCESSORSUS 6,360,259 · 2002 DUAL-MODE VLIW ARCHITECTURE PROVIDING A SOFTWARE-CONTROLLED VARYING MIX OF INSTRUCTION-LEVEL AND TASK-LEVEL PARALLELISMUS 6,317,820 · 2001 PROCESSOR ALLOCATING METHOD/APPARATUS IN MULTIPROCESSOR SYSTEM, AND MEDIUM FOR STORING PROCESSOR ALLOCATING PROGRAMUS 6,199,093 · 2001 IMAGE INQUIRY CIRCUIT CAPABLE OF COMPARING REFERENCE IMAGE AND RETRIEVAL OBJECT IMAGEUS 6,175,665 · 2001 PARALLEL PROCESSOR WITH DEBUG CAPABILITYUS 6,173,386 · 2001 METHOD OF SHORTENING BOOT UP TIME IN A COMPUTER SYSTEMUS 6,122,677 · 2000 SYSTEM FOR CONTEXT SWITCHING BETWEEN PROCESSING ELEMENTS IN A PIPELINE OF PROCESSING ELEMENTSUS 6,101,599 · 2000 SYNCHRONIZATION CIRCUIT FOR TRANSFERRING POINTER BETWEEN TWO ASYNCHRONOUS CIRCUITSUS 6,055,285 · 2000 HIERARCHICAL DUAL BUS ARCHITECTURE FOR USE IN AN ELECTRONIC SWITCHING SYSTEM EMPLOYING A DISTRIBUTED CONTROL ARCHITECTUREUS 6,052,752 · 2000 VLIW PROCESSOR WITH WRITE CONTROL UNIT FOR ALLOWING LESS WRITE BUSES THAN FUNCTIONAL UNITSUS 6,044,451 · 2000 DATA PROCESSORUS 6,023,757 · 2000

and 33 more

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