Patent US 8,612,949

Patent №

US 8,612,949

Granted

Owner

Lab

AI components

2

planning · hardware

Assignment

None on record

Dataset

AIPD

2023_r1 edition

Application

12650630

Methods and apparatuses for compiler-created helper thread for multi-threading are described herein. In one embodiment, exemplary process includes identifying a region of a main thread that likely has one or more delinquent loads, the one or more delinquent loads representing loads which likely suffer cache misses during an execution of the main thread, analyzing the region for one or more helper threads with respect to the main thread, and generating code for the one or more helper threads, the one or more helper threads being speculatively executed in parallel with the main thread to perform one or more tasks for the region of the main thread. Other methods and apparatuses are also described.

PlanningAI hardwareG06F 9/3842G06F 8/4442G06F 9/383G06F 9/3851

AI classification

AI hardware0.98
Planning0.95
Machine learning0.43
Knowledge representation0.02
Vision0.02
Natural language0.02
Evolutionary computation0.02
Speech0.00
© 2026 NYSGPT2525 LLC