BYTE-ACCURATE SCHEDULING IN A NETWORK PROCESSOR

Patent №

US 8,619,787

Granted

2013-12-31

Filed 2011

Owner

LSI CORPORATION

Lab

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

13250927

Described embodiments provide for scheduling packets for transmission by a network processor. A traffic manager generates a tree scheduling hierarchy having a root scheduler and N scheduler levels. The network processor generates tasks corresponding to received packets. The traffic manager enqueues the received task in the associated queue, the queue having a corresponding parent scheduler at each of one or more next levels of the scheduling hierarchy up to the root scheduler. Each scheduler determines one or more tasks to schedule from a given queue based on a default packet size of the packet corresponding to the task. The corresponding packet data is read from a shared memory, and, at each corresponding parent scheduler up to the root scheduler, an actual size of the packet data is updated. Scheduling weights of each corresponding parent scheduler are updated based on the actual size of the packet data.

AI hardwareH04L 49/254H04L 47/621H04L 47/623H04L 47/628H04L 49/101H04L 49/109H04L 49/506G06F 12/0813

AI classification

AI hardware1.00
Machine learning0.07
Knowledge representation0.01
Evolutionary computation0.00
Natural language0.00
Speech0.00
Planning0.00
Vision0.00

Ownership

LSI CORPORATION

assignment · 270050322

Assignors

SONNIER, DAVID, SUNDARARAMAN, BALAKRISHNAN

On an employer assignment, the assignors are typically the inventors.

© 2026 NYSGPT2525 LLC