System and Method of Signal Processing Engines with Programmable Logic Fabric

Patent №

US 8,700,837

Granted

2014-04-15

Filed 2012

Owner

CSWITCH CORPORATION

+1 more

Lab

—

AI components

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

13367246

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A high performance field programmable gate array is described with one or more signal processing engines coupled to a programmable logic fabric. Each signal processing engine includes a signal processing unit for performing specifying tasks and a bus-based configurable connection box for routing a bus-based input to a bus-based output. The signal processing unit has a floating point unit (FPU)/multiply accumulate (MAC) for computation and register files for storing information. The programmable logic fabric is coupled to the one or more signal processing engines for routing of information between the signal processing engines.

AI hardwareG06F 7/483G06F 7/5443

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AI hardware1.00

Machine learning0.45

Vision0.15

Natural language0.00

Evolutionary computation0.00

Knowledge representation0.00

Speech0.00

Planning0.00

Ownership

CSWITCH CORPORATION

assignment · 323270965

AGATE LOGIC, INC.

assignment · 323280210

Assignors

VERMA, HARE KRISHNA, GUNWANI, MANOJ, SUNKAVALLI, RAVI

On an employer assignment, the assignors are typically the inventors.

From the same owner

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Cites (23)

DEDICATED LOGIC CELLS EMPLOYING SEQUENTIAL LOGIC AND CONTOL LOGIC FUNCTIONSUS 7,417,456 · 2008 DEDICATED LOGIC CELLS EMPLOYING CONFIGURABLE LOGIC AND DEDICATED LOGIC FUNCTIONSUS 7,414,431 · 2008 DEDICATED LOGIC CELLS EMPLOYING SEQUENTIAL LOGIC AND CONTROL LOGIC FUNCTIONSUS 7,414,432 · 2008 DEDICATED LOGIC CELLS EMPLOYING SEQUENTIAL LOGIC AND CONTROL LOGIC FUNCTIONSUS 7,368,941 · 2008 DEDICATED LOGIC CELLS EMPLOYING CONFIGURABLE LOGIC AND DEDICATED LOGIC FUNCTIONSUS 7,358,765 · 2008 ARCHITECTURE FOR A CONNECTION BLOCK IN RECONFIGURABLE GATE ARRAYSUS 7,193,437 · 2007 PROGRAMMABLE LOGIC AND ROUTING BLOCKS WITH DEDICATED LINESUS 7,176,717 · 2007 CONFIGURABLE PERIPHERAL DEVICESUS 7,032,038 · 2006 FPGA WITH REGISTER-INTENSIVE ARCHITECTUREUS 7,028,281 · 2006 ARCHITECTURE AND INTERCONNECT SCHEME FOR PROGRAMMABLE LOGIC CIRCUITSUS 6,462,578 · 2002 INPUT/OUTPUT INTERCONNECT CIRCUIT FOR FPGASUS 6,204,689 · 2001 DATA PROCESSING SYSTEM AND METHOD THEREOFUS 6,085,275 · 2000 FIELD PROGRAMMABLE GATE ARRAY HAVING TESTABLE ANTIFUSE PROGRAMMING ARCHITECTURE AND METHODS THEREFORUS 6,081,129 · 2000 DPGA-COUPLED MICROPROCESSORSUS 6,052,773 · 2000 APPARATUS AND METHOD FOR A NETWORK ROUTERUS 5,991,817 · 1999 PROGRAMMABLE MULTIPLEXING INPUT/OUTPUT PORTUS 5,847,578 · 1998 WORM-HOLE RUN-TIME RECONFIGURABLE PROCESSOR FIELD PROGRAMMABLE GATE ARRAY (FPGA)US 5,828,858 · 1998 PROCESSOR HAVING A BUS INTERCONNECT WHICH IS DYNAMICALLY RECONFIGURABLE IN RESPONSE TO AN INSTRUCTION FIELDUS 5,771,362 · 1998 FIELD-PROGRAMMABLE ELECTRONIC CROSSBAR SYSTEM AND METHOD FOR USING SAMEUS 5,530,813 · 1996 METHOD AND APPARATUS FOR ROUTING MESSAGE POCKETSUS 4,598,400 · 1986 Patent US 4,807,183US 4,807,183 Patent US 5,016,163US 5,016,163 Patent US 7,185,138US 7,185,138

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