AUTOMATIC REDUCTION OF MODES OF ELECTRONIC CIRCUITS FOR TIMING ANALYSIS

Modes of a circuit are merged together to reduce the number of modes. Subsets of modes are identified such that modes belonging to each subset are mergeable. A set of modes is mergeable if every pair of modes in the set is mergeable. Constraints of modes belonging to each pair of modes are compared to determine whether two modes are mergeable. To allow two modes to be merged, a constraint is transformed such that it affects the same paths in the merged mode and the first mode but excludes paths from the second mode. Determining whether two modes are mergeable may include verifying whether a clock in one mode blocks propagation of a clock in another mode and whether a value specified in a constraint in a mode is within specified tolerance of the value of a corresponding constraint in another mode.