SEQUENCE DETECTION FOR FLASH MEMORY WITH INTER-CELL INTERFERENCE

A system including a read module and a sequence detector module. The read module is configured to read a plurality of memory cells located along a bit line or a word line of a memory array and to generate a plurality of read signals. The sequence detector module is configured to detect a sequence of data stored in the plurality of memory cells based on (i) the plurality of read signals and (ii) a plurality of reference signals associated with the plurality of memory cells. One of the plurality of reference signals associated with a first memory cell of the plurality of memory cells includes (i) a first signal and (ii) a second signal. The first signal is free of interference from a second memory cell adjacent to the first memory cell along the bit line or the word line. The second signal includes interference from the second memory cell.