PERFORMING A CYCLIC REDUNDANCY CHECKSUM OPERATION RESPONSIVE TO A USER-LEVEL INSTRUCTION
Patent №
US 8,713,416
Granted
2014-04-29
Filed 2013
Owner
INTEL CORPORATION
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
13796032
In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.
AI hardwareG06F 11/1004G06F 9/30003G06F 9/30018G06F 9/30032G06F 15/76G06T 1/20H03M 13/00H03M 13/09+3 more
AI classification
AI hardware0.94
Natural language0.00
Vision0.00
Speech0.00
Knowledge representation0.00
Evolutionary computation0.00
Machine learning0.00
Planning0.00
Ownership
INTEL CORPORATION
assignment · 309900480
Assignors
KING, STEVEN R., BERRY, FRANK L., KOUNAVIS, MICHAEL E.
On an employer assignment, the assignors are typically the inventors.
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