CONFIGURABLE LOGIC INTEGRATED CIRCUIT HAVING A MULTIDIMENSIONAL STRUCTURE OF CONFIGURABLE ELEMENTS

Patent №

US 8,726,250

Granted

2014-05-13

Filed 2010

Owner

—

Lab

—

AI components

hardware

Assignment

None on record

Dataset

AIPD

2023_r1 edition

Application

12720898

Programming of modules which can be reprogrammed during operation is described. Partitioning of code sequences is also described.

AI hardwareG06F 15/80G06F 8/433G06F 8/45G06F 15/7867

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Cites (329)

Methods and apparatus for simulation speedupUS 8,645,927 · 2014 METHOD FOR THE TRANSLATION OF PROGRAMS FOR RECONFIGURABLE ARCHITECTURESUS 7,996,827 · 2011 POLYMORPHOUS COMPUTING FABRICUS 7,873,811 · 2011 METHOD FOR PROCESSING DATAUS 7,657,877 · 2010 I/O AND MEMORY BUS SYSTEM FOR DFPS AND UNITS WITH TWO- OR MULTI-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURESUS 7,650,448 · 2010 LOGIC CELL ARRAY AND BUS SYSTEMUS 7,595,659 · 2009 METHOD AND APPARATUS FOR UNIVERSAL PROGRAM CONTROLLED BUS ARCHITECTUREUS 7,382,156 · 2008 METHOD FOR DEBUGGING RECONFIGURABLE ARCHITECTURESUS 7,266,725 · 2007 SYSTEM AND METHOD FOR PREPARING SOFTWARE FOR EXECUTION IN A DYNAMICALLY CONFIGURABLE HARDWARE ENVIRONMENTUS 7,249,351 · 2007 MECHANISM FOR PROVIDING EARLY COHERENCY DETECTION TO ENABLE HIGH PERFORMANCE MEMORY UPDATES IN A LATENCY SENSITIVE MULTITHREADED ENVIRONMENTUS 7,216,204 · 2007 METHOD FOR TRANSLATING PROGRAMS FOR RECONFIGURABLE ARCHITECTURESUS 7,210,129 · 2007 PARAMETERIZED GRAPHS WITH CONDITIONAL COMPONENTSUS 7,164,422 · 2007 DEBUGGING AND PERFORMANCE PROFILING USING CONTROL-DATAFLOW GRAPH REPRESENTATIONS WITH RECONFIGURABLE HARDWARE EMULATIONUS 7,155,708 · 2006 METHOD AND APPARATUS FOR CYCLE-BASED COMPUTATIONUS 7,036,114 · 2006 EFFICIENT SPLITTING AND MIXING OF STREAMING-DATA FRAMES FOR PROCESSING THROUGH MULTIPLE PROCESSING MODULESUS 7,007,096 · 2006 3D GRAPHICS RENDERING WITH SELECTIVE READ SUSPENDUS 6,977,649 · 2005 DISPLAYING VARIABLE USAGE WHILE DEBUGGINGUS 6,961,924 · 2005 SYSTEM AND A METHOD FOR CHECKING LOCK STEP CONSISTENCY BETWEEN AN IN CIRCUIT EMULATION AND A MICROCONTROLLER WHILE DEBUGGING PROCESS IS IN PROGRESSUS 6,922,821 · 2005 CUSTOM CODE PROCESSING IN PGA BY PROVIDING INSTRUCTIONS FROM FIXED LOGIC PROCESSOR PORTION TO PROGRAMMABLE DEDICATED PROCESSOR PORTIONUS 6,886,092 · 2005 FAULT TOLERANT OPERATION OF RECONFIGURABLE DEVICES UTILIZING AN ADJUSTABLE SYSTEM CLOCKUS 6,874,108 · 2005 ADAPTIVE SCHEDULING OF FUNCTION CALLS IN DYNAMIC RECONFIGURABLE LOGICUS 6,871,341 · 2005 DATA PROCESSING SYSTEMUS 6,859,869 · 2005 A METHOD OF PARTIAL RECONFIGURATION OF A PLD IN WHICH ONLY UPDATED PORTIONS OF CONFIGURATION DATA ARE SELECTED FOR RECONFIGURING THE PLDUS 6,836,842 · 2004 MULTIPLE LOGICAL INTERFACES TO A SHARED COPROCESSOR RESOURCEUS 6,829,697 · 2004 METHOD AND APPARATUS FOR VARYING INSTRUCTION STREAMS PROVIDED TO A PROCESSING DEVICE USING MASKSUS 6,820,188 · 2004

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Cited by (3)

PROGRAMMABLE INTERFACE TO IN-MEMORY CACHE PROCESSORUS 10,705,967 · 2020 METHODS AND SYSTEMS FOR RUN-TIME HARDWARE CONFIGURATION CHANGE MANAGEMENTUS 9,483,282 · 2016 Patent US 11,151,046US 11,151,046

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